Introduction to SystemVerilog and the VMM Framework

Client required team be educated on applying VMM and the SVTB language to develop a series of new Verificaiton Platforms for various storage based ASICs and FPGAs

  • Architect of multiple Verification Platforms. 
  • Developed internal forum for discussions to common solutions.
  • Educated staff on how to develop assertions and functional coverage.

Emulation with a Rocket Guidance System.

Client required a hardware in the loop emulation of a rocket guidance system to allow them to perform Independent Software Validation.

  • Architect of 2 different emulation systems which used Windows base PC's with external PCI Chassis. 
  • Allowed ISV to inject both soft and hard faults to test the recovery of the Software.
  • Desired timing accurate and required actual flight processors to be used.

ASIC Emulation with a Custom FPGA Design.

Client required a repeatable methodology to move ASIC design code into an custom FPGA emulation system.  Challenges included:

  • Emulation PCB already designed with preliminary estimates from the ASIC engineers. 
  • Pin locking of all FPGAs.
  • Desired cycle accurate.
  • ASIC code could not endure any modifications.

Submitted a  project as a case study for Design SuperCon 98.

Development of Full Custom Imaging Chip.

Member of development team which designed a full custom imaging chip for a leading edge Colorado company.  Duties included:

  • development of custom synthesis cell library
  • verification of SPICE base simulations
  • synthesis of entire chip
  • verification of final gate level netlist.

Similar design for same customer but concentrated on the control logic for the design.  Customer required design in two weeks from concept to finished netlist.  With 6 man-weeks of effort the netlist was delivered. 


Provided over 45 days of hands on VHDL training both on customer sites and off-site locations.  
Classes included:

  • 1 day seminars
  • 2 days hand-on synthesis training
  • 3-day VHDL introduction courses an
  • 5-day VHDL complete courses.

Provided 3 day schematic entry training to 60 engineers.  Involved was the development of course material, setup of equipment and delivery of the material. 

3-D Graphics

Lead a team of engineers and consultants in the development of a next generation 3-D simulation system which involved shrinking a refrigerator size cabinet into a single 12x9 PCB with four distinct ASICs.  Responsible for team dynamics, communication, tools, validation and overall success of the design.

SuperCon paper  "Using VHDL Abstract Data Types to Design a 3-D Graphics Pipeline"  describes our unusual approach to solving the problem. 

Client Engagements